Appeal No. 2005-2273 Page 3
Application No. 10/319,026
a vector transfer unit coupled to the register tile, wherein the vector
transfer unit comprises a dual port memory for storing vector data and a
vector transfer execution unit coupled to the dual port memory, wherein
the vector transfer execution unit comprises a vector transfer instruction
queue for storing load/store and move vector data instructions;
wherein the vector transfer execution unit transfers vector data
between a main memory and the dual port memory in response to the
vector transfer execution unit executing a load/store vector data instruction
stored in the vector transfer instruction queue;
wherein the vector transfer execution unit transfers vector data
between the dual port memory and one or more registers of the register
file in response to the vector transfer execution unit executing a move
vector data instruction stored in the vector transfer instruction queue.
Claims 21, 22, and 26 stand rejected under 35 U.S.C. § 103(a) as obvious over
U.S. Patent No. 5,689,653 ("Karp") and U.S. Patent No. 5,487,156 ("Popescu"), with a
definition of the term "cache" from the Free On-Line Dictionary of Computing
("FOLDOC") cited as extrinsic evidence. Claims 23, 24, 25a, and 25b stand rejected
under § 103(a) as obvious over Karp; Popescu; and U.S. Patent No. 4,594,682
("Drimak"), with FOLDOC cited as extrinsic evidence.
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