Appeal No. 2005-2273 Page 4
Application No. 10/319,026
II. OPINION
Our opinion addresses the rejections in the following order:
• Examiner's rejections
• Board's rejection.
A. EXAMINER'S REJECTIONS
"Rather than reiterate the positions of the examiner or the appellant in toto, we
focus on the point of contention therebetween." Ex parte Kaysen, No. 2003-0553,
2004 WL 1697755, at *2 (Bd.Pat.App & Int. 2004). The examiner admits, "Karp et al.
did not teach that the vector transfer execution unit comprised a vector transfer
instruction queue for storing the instructions." (Examiner's Answer at 5.) Finding that
"Popescu et al. taught an instruction queue for storing instructions awaiting execution
(fig. 2, 11)," (id.), he offers the following assertion.
[T]emporary imbalances between the rate that instructions are issued and
executed arise because Karp et al. implements a cache memory (see
col. 3 lines 28-29, col. 4 lines 5-9, and claim 1, lines 2-3). As is shown by
the extrinsic evidence of the FOLDOC definition of cache, a cache is
accessed more quickly than main memory: ''The cache is built from faster
memory chips than main memory so a cache hit takes much less time to
complete than a normal memory access.'' As it is impossible to issue an
instruction before it is fetched from memory, the fact that fetching of
instructions will have temporary rate imbalances (because a hit in cache
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