Appeal No. 2005-2273 Page 5
Application No. 10/319,026
will be satisfied much more quickly than a miss in cache, see FOLDOC
definition) results in the issue rate also having temporary rate imbalances.
(Id. at 10.) Based on this assertion, the examiner concludes, "addition of a queue as
taught by Popescu to smooth those temporary rate imbalances would have been
obvious to one of ordinary skill in the art at the time of invention." (Id.) The appellant
argues, "An imbalance between the rate instructions are issued and the rate issued
instructions are executed depends on the speed at which instructions are executed.
If Karp employs a processor that executes instructions faster than instructions are
issued, there will be no adverse rate imbalance regardless of whether the instructions
issue from a cache memory or from normal memory." (Reply Br. at 3)
"In addressing the point of contention, the Board conducts a two-step analysis.
First, we construe the independent claim at issue to determine its scope. Second, we
determine whether the construed claim would have been obvious." Ex parte Sehr,
No. 2003-2165, 2005 WL 191041, at *3 (Bd.Pat.App & Int. 2004).
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