Appeal No. 2005-2273 Page 9
Application No. 10/319,026
Karp further explains that an "instruction issue unit 56 decodes instructions of a
currently executing program read by the processor 22 (FIG. 1) from the memory 24
(FIG. 1) and issues control signals directing execution of corresponding operations
within the processor. Vector data transfers between the memory hierarchy 46
and . . . vector buffers 50-52 are initiated by the instruction issue unit 56 in
response to vector request instructions in the currently executing program.
These vector request instructions specify information identifying the vector in
the memory hierarchy 46 which is to be the subject of a vector data transfer." Col. 4,
ll. 46-56.
Turning to FOLDOC, it is uncontested that "a cache hit takes much less time to
complete than a normal memory access." P. 1. Nonetheless, we are unpersuaded that
"temporary imbalances between the rate that instructions are issued and executed,"
(Examiner's Answer at 10), necessarily arise in Karp and would be so recognized by
persons of ordinary skill in the art. To the contrary, we agree with the appellant that
"[i]f Karp employs a processor that executes instructions faster than instructions are
issued, there will be no adverse rate imbalance regardless of whether the instructions
issue from a cache memory or from normal memory." (Reply Br. at 3) In other words,
the reference's processor 22 may execute its vector instructions fast enough to preclude
any rate imbalance regardless of whether the instructions are fetched from its
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