Appeal No. 2006-1049
Application No. 09/667,826
53. An infrared focal plane array, comprising:
a plurality of detector elements configured in a two dimensional array; and
a readout circuit electrically coupled to said plurality of detector elements
and structurally integrated therewith, said readout circuit comprising:
a sample and hold capacitor;
means for biasing the detector elements so as to provide an analog detection
signal from each detector element corresponding to the infrared radiation
incident thereon, wherein the analog detection signal is a voltage signal
provided at a sample node coupled to the sample and hold capacitor; and
means for correcting the analog detection signal from each detector element
by a discrete offset correction and providing a corrected analog detection
signal, wherein the discrete offset correction varies from detector element to
detector element and comprises an offset correction voltage added to, or
subtracted from, the analog detection signal, wherein said means for
correcting subtracts or adds a variable amount of charge from said sample
and hold capacitor to provide a corrected voltage signal at said sample node,
and wherein said means for correcting comprises a plurality of circuit
elements connected between said sample node and a reference voltage and a
corresponding plurality of switches coupled in series with each respective
circuit element and said reference voltage, wherein said plurality of switches
selectively provide a desired amount of discrete offset correction for each
detector element.
54. An infrared focal plane array as set out in claim 53, wherein said readout
circuit further comprises means for controlling said means for correcting so as to
selectively open and close said plurality of switches in a time multiplexed manner
during readout of a plurality of separate detector elements.
55. An infrared focal plane array as set out in claim 53, wherein said detector
elements comprise microbolometer detector elements.
56. An infrared focal plane array as set out in claim 53, wherein said readout
circuit further comprises a differential amplifier having first and second inputs, the
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