Ex Parte Zandveld et al - Page 3




               Appeal No. 2006-1303                                                                                                  
               Application No. 10/000,667                                                                                            


                       Claims 6, 7, 9, 22, and 23 stand rejected under 35 U.S.C. §102 (b) as anticipated by                          
               Davis.                                                                                                                
                       Claims 10, 11, 13-15, 18, 19, 21, 24, and 25 stand rejected under 35 U.S.C. §103 as                           
               unpatentable over Davis in view of Colwell.                                                                           
                       Reference is made to the brief and answer for the respective positions of appellant and the                   
               examiner.                                                                                                             
                                                      OPINION                                                                        
                       A rejection for anticipation under section 102 requires that the four corners of a single                     
               prior art document describe every element of the claimed invention, either expressly or                               
               inherently, such that a person of ordinary skill in the art could practice the invention without                      
               undue experimentation.  In re Paulsen, 30 F.3d 1475, 1478-79, 31 USPQ2d 1671, 1673 (Fed. Cir.                         
               1994).                                                                                                                
                       The examiner’s position with regard to independent claims 6 and 22 is that Davis’s                            
               Figure 6, depicting a reduced instruction set computer (RISC) type architecture, comprises an                         
               interleaved instruction memory 126 including a plurality of independently addressable memory                          
               banks (220 and 230 shown in Figure 7) for storing a set of logically successive instructions                          
               (noting that successive instructions are alternately stored in memory banks 220 and 230).  The                        
               examiner contends that the first memory bank 220 stores a first instruction of the set of logically                   




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