Appeal No. 2006-1595
Application No. 09/798,484
Regarding the third logic limitation, appellants emphasize that Burgoon does not
teach nor suggest a third logic that identifies connections within the source code
model to be enabled or disabled [brief, page 12; emphasis in original]. The
examiner responds that Burgoon’s initialization functions that set the interface
pointers, installing the packet handler module, and calling the initialization
functions after the simulation controller determines which functions should be in
C and Verilog respectively on Page 5 of Burgoon correspond to the third logic
limitation [answer, page 31]. Regarding the fourth logic limitation, the examiner
contends that Burgoon’s disclosure on Page 3 of “read[ing] the initialization files
that define which models are represented in C and which are described in
Verilog, and configur[ing] the simulator accordingly” corresponds to the fourth
logic limitation [answer, pages 32 and 33].
Appellants also argue that Parson does not disclose first logic identifying
hierarchy paths within the source code model as claimed [brief, page 14].
Appellants further argue that Parson does not disclose second logic that
identifies hierarchy paths within the source code model that corresponds to
hierarchy paths in the HDL model [brief, page 15]. The examiner responds by
citing various passages within the disclosure of Parson that teach hierarchical
paths in the hardware, the source code model, the HDL model, and the
correspondence among them [answer, pages 35 and 36]. The examiner also
reiterates that the specification does not describe the logic, procedure, or
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