Appeal No. 2006-1595
Application No. 09/798,484
determines which functions should be in C and Verilog respectively on Page 5 of
Burgoon reasonably correspond to the third logic limitation. Significantly, the
claimed third logic limitation requires that the logic identify connections within the
source code model to enable or disable [emphasis added]. Setting interface
pointers and calling initialization functions after the controller determines which
functions should be in C and Verilog respectively in Burgoon does not reasonably
teach nor suggest identifying connections within the source code model to enable
or disable as claimed. For at least this reason, we will not sustain the examiner’s
obviousness rejection.
Furthermore, the secondary reference, Parson, discloses a simulation
model using object-oriented programming that, among other things, includes a
C++ model constructor that creates a C++ model object hierarchy that is
isomorphic to a corresponding hierarchical netlist structure [Parson, col. 7, lines
37-43]. Although Parson pertains to simulation modeling that incorporates the
basic structure and notation as netlist languages, ultimately the model is an
object-oriented program with aspects that are structurally equivalent to netlist
languages [see, e.g., Parson, col. 3, lines 52-58]. Although Parson does teach
maintaining subcircuit representation hierarchy as the examiner indicates, we
see no reason why the skilled artisan would combine the isolated teachings of
the object-oriented program of Parson with the mixed-language simulation of
Burgoon. In short, we find no reasonable rationale or motivation to combine the
references in the manner suggested by the examiner apart from hindsight
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