Appeal No. 2006-1595
Application No. 09/798,484
algorithm used to identify hierarchy paths within the source code model that
correspond to hierarchy paths in the HDL model [answer, pages 36 and 37].
Appellants further argue that the examiner’s combination of Parson and
Burgoon is improper, particularly the examiner’s motivation to combine the
references [brief, pages 15-18]. The examiner responds that the skilled artisan
interested in mixed-language simulation would be motivated to combine Burgoon
and Parson since both references pertain to (1) simulating integrated circuits,
and (2) source code and HDL simulation models and their correspondence
[answer, page 38].
We will not sustain the examiner’s rejection of independent claims 1, 12,
and 22. Burgoon discloses a mixed-language simulator that can migrate models
from the C world into a Verilog simulation [Burgoon, page 4; Fig. 3]. Such a
migration includes: (1) a C interface module that provides versions of the model’s
interface functions to the Verilog world for evaluation; (2) a Verilog interface
module that receives packets and manipulates signals in the Verilog world; and
(3) a packet handler module that allows the Verilog world to generate requests
for the C world [Burgoon, page 5].
We agree with appellants that Burgoon fails to reasonably teach or
suggest third logic identifying connections within the source code model to be
enabled or disabled as claimed. We disagree with the examiner that Burgoon’s
initialization functions setting the interface pointers, installing the packet handler
module, and calling the initialization functions after the simulation controller
18
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