Appeal No. 2006-1729
Application No. 10/107,628
tree is that any combination of odd number of errors on
its inputs propagates to their outputs, and any
combination of even number of errors remains
undetected.
At page 4, paragraph 0041, Rajski discloses the following:
FIG. 9 shows another embodiment of a selective
compactor 80 that is coupled to scan chains 82. The
selective compactor includes a selector circuit 84,
which is identical to the selector circuit 46 described
in relation to FIG. 8. The selective compactor 80 also
includes a time compactor 84, which is well understood
in the art to be a circular compactor. The time
compactor includes multiple flip-flops 86 and XOR gates
88 coupled in series. A reset line 90 is coupled to
the flip-flops 86 to reset the compactor 84. The reset
line may be reset multiple times while reading the scan
chains. Output register 92 provides a valid output of
the compactor 84 upon activation of a read line 94.
With the above discussion in mind, we find that the Rajski
reference teaches a method for selectively compacting test
responses scan chains into a compressed output. Particularly, as
depicted in figure 9, Rajski teaches a plurality of scan chain
inputs (82) that are fed into a compactor (80) to produce a
plurality of outputs (92). Rasjki also teaches that each of the
plurality of inputs is coupled to at least one of the plurality
of outputs via an X-OR gate (88). One of ordinary skill in the
art would have readily observed from Rajski’s illustration of the
coupling of scan chain inputs with scan chain outputs through X-
OR gates that each of the inputs are coupled to the outputs in a
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