Appeal No. 2006-1729
Application No. 10/107,628
compressed outputs (92). Rajski also teaches that the compactor
comprises a plurality of Ex-OR gates. Next, we find that Hong is
relied upon for its teaching of using nonzero binary values as
inputs to an EX-OR tree during the normal operation of a logic
circuit. One of ordinary skill in the art would have duly
recognized that Rajski’s teaching of implementing the compactor
with EX-OR gates amounts to the compactor having a plurality of
binary inputs and outputs, which could be represented in the form
of a matrix. Even though such mathematical characterizations of
digital logic circuits are somewhat common, they are not
necessarily the sole and only manner of characterizing such
circuits. Thus, at the time of the invention, without any
specific teaching or suggestion4 to characterize the inputs and
outputs of the compactor in the form of a matrix, Rajski would
not have necessarily led the ordinarily skilled artisan to this
particular characterization of the compactor. Unfortunately,
Hong does not remedy such deficiencies. Consequently, we find
error in the Examiner’s stated position, which concludes that the
combination of Rajski and Hong teaches a compactor characterized
by a binary matrix having a row for each of the plurality of
circuit elements and a column for each compactor output. It is
4 We note that such a suggestion could have been obtained from the disclosure
of Ivanov as provided in the discussion of representative claim 1 above.
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