Appeal No. 2006-1729
Application No. 10/107,628
[P]roviding a compactor characterized by a binary
matrix having a row for each of a plurality of circuit
elements and a column for each compactor output.
We also note that claim 22 reads in part as follows:
[A]t least one exclusive OR gate coupled between each
input and at least one output; and each input being
coupled to said outputs differently.
At page 4, lines 12 through 18, Appellants’ specification states:
A compactor design can be represented as a binary
matrix (matrix with only zeros and ones) with n rows
and m columns. Each row corresponds to a scan chain
and each column corresponds to a compactor output. The
entry in row i and column j of the binary matrix is 1,
if the ith scan chain output is exclusive OR-ed to
generate the jth output of the compactor; the matrix
entry is 0 otherwise.
Further, at page 5, lines 17 through 20, Appellants’
specification states:
As shown in FIG. 2, the exclusive OR gates 14 are
arranged such that there is at least one exclusive OR
gate 14 coupled between each input to the compactor 12a
and at least one output from the compactor. Each input
is also coupled to the outputs differently in
accordance with one embodiment of the present
invention.
Thus, representative claim 1 does require a compactor
characterized by matrix having a row for each of the plurality of
circuit elements and a column for each of the plurality of
outputs. Similarly, representative claim 22 does require an Ex-
7
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Next
Last modified: November 3, 2007