Appeal No. 2006-1729
Application No. 10/107,628
Invention
Appellants’ invention relates generally to a method and
device for facilitating the design of an integrated circuit by
reducing the number outputs to thereby keep the number of circuit
pins to a minimum. First, a response compactor (12a) receives an
n plurality of scan chain inputs (10), and produces an m
plurality of scan chain outputs, where the number of scan chain
inputs far exceeds the number of scan chain outputs. The response
compactor (12a) is characterized by a binary matrix having a row
for each of the plurality of scan chain inputs. All the rows are
non-zero and unique. The binary matrix also includes a column
for each of the plurality of scan chain outputs such that said
plurality of inputs and outputs are connected through a plurality
of exclusive-OR gates.
Claims 1 and 22 are representative of the claimed invention
and are reproduced as follows:
1. A method comprising:
providing a compactor characterized by a binary
matrix having a row for each of a plurality of
circuit elements and a column for each compactor
output; and
making all of the matrix rows non-zero and different
from each of the other rows.
2
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