Appeal No. 2006-2707
Application No. 09/749,792
down to a rate that can reduce the amount of power dissipated in
the processor.
It is our view that one of ordinary skill in the art would
have duly recognized that Georgiou’s teaching of a clock selector
that selects a reduced clock frequency in response to an
indication that the processor is overheating amounts to the
claimed limitation of a PDL input that determines the rate of
reduction of a temperature-related frequency. The ordinarily
skilled artisan would have readily been apprised of the fact that
by selecting a reduced clock frequency to prevent further power
dissipation in the processor, the frequency selector disclosed in
Georgiou must necessarily select a reduced frequency rate that is
capable of reducing the temperature of the processor.
As to McDermott, his teaching of determining the rate of
change for advancing or retarding the output frequency is limited
to improving the performance of a PLL circuit, notwithstanding
the temperature of the processors used such inter-chip
communications. We find, however, that the Examiner’s reliance
upon McDermott for the cited teaching was cumulative since
Georgiou discloses such teaching. It is our view that since
Georgiou teaches a performance demanding level input for
determining the rate of reduction of the temperature-related
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