Appeal No. 2006-2707
Application No. 09/749,792
We note at paragraph 20, Appellant’s specification states
the following:
[0020] The performance demanding level
signal (PDL) 311 is an input signal used by
the frequency reduction circuit 305 to
determine the level of sensitivity (or
aggression) used for frequency reduction. If
PDL signal 311 is asserted (e.g., value of
"1"), then frequency reduction cannot be
aggressive and instead fine granularity must
be used (e.g., [fraction (1/15)] reduction
from normal clock frequency) for reducing the
normal clock frequency. Alternatively, if
PDL signal 311 is not asserted (e.g., value
of "0"), then frequency reduction can be
aggressive and higher percentages of
frequency reduction (e.g., close to 50%
reduction from normal clock frequency) may be
used for reducing the normal clock frequency.
Advantageously, the PDL signal 311 can be
used as a form of hardware performance
profiling for system components
interconnected to processor architecture 300.
Thus, the claim does require a performance demanding level
input for determining the rate of reduction of the temperature-
related frequency.
Now, the question before us is what Georgiou and McDermott
would have taught to one of ordinary skill in the art? To answer
this question, we find the following facts:
8
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Next
Last modified: November 3, 2007