Appeal No. 2006-2707
Application No. 09/749,792
acceptable temperature TOK (i.e., an overheat
condition). During the next cycle of clock
44, the clock arbiter 51 again latches in the
overheat signal from temperature sensing
circuit 49. If the overheat signal is still
active, indicating that the overheat
condition still exists, then clock arbiter 51
assumes the down state as shown by path 77 in
FIG. 6, and activates the down output.
[Emphasis added].
Ko is concerned with managing the amount of power consumed
in a single chip data processing device. Particularly, Ko
teaches a temperature sensing circuit (49) that determines the
temperature of a processor and forwards an overheat signal to a
clock arbiter (51), which in turn activates a corresponding
output signal of the clock arbiter that selects a lower clock
frequency rate capable of reducing the amount of power dissipated
in the processor. One of ordinary skill in art would have
readily recognized that Ko’s teaching of reducing the clock
frequency in response to an indication of the processor being
overheated amounts to the claimed limitation of a PDL input that
determines a rate of reduction of the temperature-related
frequency. In addition, as noted in the discussion of claim 1
above, such limitation is also taught by Georgiou. In
consequence, we do not find error in the examiner’s stated
position, which concludes that the combination of Ko, Georgiou
and McDermott teaches the claimed limitation of a performance
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