Appeal 2007-0357
Application 10/180,862
Although the claimed arithmetic portion is stated by the Examiner to
be a part of the digital controller of the Intel reference, it goes without saying
that the admitted prior art already has a computer unit including an
arithmetic portion as well as the admitted prior art bridge as explained and
noted again at page 5 of the Answer. It is worthy of further note here that
the Examiner has made note at this page of the Answer of the confirming
teachings in Miller and Liu even though these references were not directly
relied upon to formulate a rejection of the claims on appeal. The Examiner
appears to be relying upon them to further explain and to show inherency of
the Intel reference within the provision of MPEP 2131.01. They confirm
and expand upon the inherent capabilities of the digital controller of Intel to
the point of explaining that this element may in part be construed to be the
claimed bridge of claims 5 through 9 and 18 through 20. These references
confirm the use of a PCI bus, the use of a GPIO pin which appears to
correspond to the earlier-noted GPO output from the claimed bridge, and
their reliance upon the Examiner’s relied upon Intel reference as prior art to
both Miller and Liu. Figures 1A, 1B, 2A, and 2B of Liu confirm the use of
mother boards and daughter cards as indicated earlier as a part of
Appellants’ admitted prior art as well as the use of the bridges noted earlier.
The claimed PCI bus and the Intel reference are also noted and relied upon
in this reference. The bottom of column 5 indicates that the PCI bus
controller chipset was known in the art to include so-called South bridges
and North bridges.
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