Appeal 2007-0457
Application 10/652,267
2. As depicted in figure 2, the NIC (250) includes a TCP enabled
Ethernet controller (TEEC) (270), which in turn includes a Tx elastic buffer3
(280) and an Rx elastic buffer (290) for respectively storing outgoing and
incoming packets. (Specification 14).
3. Upon receiving a packet from the Ethernet (260), TEEC processes the
incoming packet without reassembly, and temporarily buffers the packet in
the internal elastic buffer (290) before forwarding the packet to the host
interface (240). (Specification 14).
4. The host memory subsequently receives the dispatched packet via the
memory controller (220). (Specification 14).
The Prior Art Relied upon
5. Boucher(2) discloses a network interface device (102) that includes a
register (112), a buffer (2114) and a DMA engine for directly writing a
multi-packet message into the memory of a computer host (100) without
TPC or IP headers. (Col. 5, ll. 40-62).
6. Boucher(1) discloses a system for accelerated data transfer and
offloading between a host computer (20) and an intelligent network interface
card (INIC) (200). (Col. 24, ll. 60-67).
7. As depicted in figure 21, the INIC (200) includes an ASIC chip (400),
a DRAM (460) and a buffer (2114). (Col. 24, l. 61- col. 25, l. 5).
3 Appellants’ Specification defines an elastic buffer as a small (e.g. 64 KB)
on chip packet buffer utilized to provide elasticity. (Specification 11,
paragraph 39).
5
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