Appeal 2007-0457
Application 10/652,267
8. The ASIC chip, in turn, includes transmit sequencers TXSEQ (2104)
and RXSEQ (2105) for respectively handling outgoing and incoming data
packets. (Col. 25, ll. 9-10).
9. Further, as depicted in figure 22, the receive sequencer RXSEQ
(2105) synchronizes and assembles incoming packet data before the packet
is transferred to the host. (Col. 25, ll. 17-27).
10. Particularly, the RXSEQ (2105) uses a packet synchronization
sequencer (2201) for instructing the data synchronization buffer4 (2200) to
load a receive byte. (Col. 25, ll. 17-27).
11. Then, it uses a packet processing sequencer (2204) to determine data
availability in the sync buffer (2200) and subsequently uses a packet
processing sequencer (2204) to instruct the data assembly register (2202) to
load a byte of data from sync buffer (2200). (Col. 26, l. 61- col. 27, l. 35).
12. RXSEQ then transfers the synchronized packet data from its internal
buffer (2217) to an external buffer (2114) in the DRAM (460). (Col. 27, ll.
36-38).
13. After all packet data has been transferred to buffer 2114, the packet
processing sequencer (2204) creates a summary (2224) indicating whether
the packet should be put on a fast path or a slow path for transfer to the host.
(Col. 29, ll. 6-19).
4 The data synchronization buffer is four bytes deep. (Col. 26, ll. 64-65).
Therefore, it qualifies as an elastic buffer (i.e. not a multi-megabyte memory
that is utilized for packet reordering reassembly or retransmission, as defined
in Appellants’ Specification, 11).
6
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Last modified: September 9, 2013