Appeal 2007-0828
Application 10/456,455
encircles” the upper surface of the interposer to form a recess, as recited by
instant claim 1.
In any event, Appellants do not contest the finding that the references
teach a “perimeter wall” as claimed. Appellants argue, however, that the
references do not teach the claimed electrical contact pads, which the
Examiner contends is met by Lin ′999.
The Examiner reads the (claim 1) first set of alternate electrical
contact pads on bond posts 20 (Lin ′999 Fig. 3) and the first lower electrical
connection pad on conductive terminal pad 32. The Examiner finds that
these pads are “electrically connected,” as claimed, because electrical
current passes through bumps 34 and vias/traces 22, 18 to pads 20. Pads 20
are, in turn, electrically connected to die pads on chip 42 via bonding wires
60, 62. (Answer 3.)
Appellant submits that such an electrical connection would require
that bond pads 20 of Lin ′999 be “electrically connected” to one another
through the semiconductor die 42. In Appellant’s view, the semiconductor
die would cease to be an operable device when electrical shorts are provided
between the bond pads 20 through the semiconductor die 42. (Reply Br. 5.)
As known in the art, a semiconductor die typically
includes relatively many bond pads configured to carry
signal voltages to individual components of the
integrated circuit contained within the die, a relatively
few bond pads configured for supplying a power voltage
to the die, and a relatively few bond pads configured for
supplying a ground voltage to the die. Appellant admits
that it may be feasible to electrically connect different
power bond pads 20 through the semiconductor die 42,
or different ground bond pads 20 through the
semiconductor die 42 without destroying or precluding
operation of the device. Lin 999 does not, however,
4
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 Next
Last modified: September 9, 2013