Appeal 2007-1097
Application 10/230,593
1 The Examiner rejected all of the claims under 35 U.S.C. § 102(b) as
2 being anticipated by Gupta et al.
3 U.S. Patent 5,910,453 issued to Gupta et al. on June 8, 1999
4 (hereinafter “Gupta”).
5 Gupta is prior art under 35 U.S.C. § 102(b).
6 B. ISSUE
7 The issue is whether the Appellant has sustained its burden of
8 showing that the Examiner erred in rejecting claims 1, 8-11, and 18-28 under
9 35 U.S.C. § 102(b) as being anticipated by Gupta.
10 C. FINDINGS OF FACT
11 The following findings of fact are believed to be supported by a
12 preponderance of the evidence. Additional findings of fact as necessary
13 appear in the Analysis portion of the opinion.
14 1. Background of the invention
15 Integrated circuits are typically fabricated on a wafer surface through
16 any number of manufacturing processes, such as layering, doping, and
17 patterning. Specification 4:1-2.
18 One commonly used patterning technique is photolithography. In
19 implementing photolithography techniques, a pattern may be formed using a
20 photomask to expose certain regions of a radiation sensitive material, such
21 as a photoresist or resist, to a certain wavelength of light. Specification
22 4:20-5:1.
23 An anti-reflectant coating (ARC) layer, such as a bottom anti-
24 reflectant coating (BARC) layer may be implemented underneath the resist
25 to enhance the photolithography process. The BARC layer is used to absorb
26 the radiation generated by the energy source. By providing a layer for
2
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