Appeal 2007-1293
Application 10/745,124
time constant sufficient to prevent single event transients from adversely impacting
the logic device output. Appellant reasons that neither Lieder nor Yanagihara
teach or suggest the claimed RC delay circuit has a time constant sufficient to
prevent a single event transients from adversely affecting the desired logic device.
(Br. 17.)
The Examiner contends that the rejection of claims 6 through 8 and 11 is
proper. The Examiner’s statement discussed above with respect to claim 1 is
applied to this rejection of claims 6 through 8 and 11.
Thus, similar to claim 1, Appellant’s contentions present us with the issue of
whether Lieder teaches an RC delay circuit which has a time constant sufficient to
prevent single event transients from adversely affecting the logic circuit as recited
in independent claim 6 and the claims grouped therewith, claims 7, 8, and 11.
ANALYSIS
RELATED TO OBVIOUSNESS REJECTIONS
BASED UPON LIEDER
Independent claim 6 recites an RC delay circuit coupled to the comparator
output … wherein the RC delay circuit has an RC time constant sufficient to
prevent single event transients from adversely affecting the logic device output.”
This limitation is virtually identical to the limitations directed to the RC delay
circuit discussed above with respect to claim 1. As discussed above in our analysis
of the anticipation rejection of claim 1, we find that Lieder anticipates this
limitation. As Appellant has not contented the rejection is improper for any other
reason, we sustain the Examiner’s rejection of claims 6 through 8 and 11 for the
reasons discussed supra with respect to the Examiner’s anticipation rejection of
independent claim 1.
11
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