Ex Parte Nash - Page 12

             Appeal 2007-1293                                                                                         
             Application 10/745,124                                                                                   



                                                      ISSUES                                                          
                                RELATED TO OBVIOUSNESS REJECTIONS                                                     
                                           BASED UPON KONOPKA                                                         

                    On pages 15 and 16 of the Brief, Appellant contends that the Examiner’s                           
             rejection of claims 6 through 8 as being obvious over Konopka and Yanagihara is                          
             in error.  Specifically, Appellant argues that claim 6 recites a RC delay circuit                        
             which has an RC time constant sufficient to prevent single event transients from                         
             adversely impacting the logic device output.   Appellant reasons that neither                            
             Konopka nor Yanagihara teach or suggest the claimed RC delay circuit has a time                          
             constant sufficient to prevent a single event transients from adversely affecting the                    
             desired logic device.  (Br. 16.)                                                                         
                    The Examiner contends that the rejection of claims 6 through 8 is proper.                         
             The Examiner’s statement discussed above with respect to claim 1 is applied to this                      
             rejection of claims 6 through 8.                                                                         
                    Thus, Appellant’s contentions present us with the issue of whether Konopka                        
             teaches an RC delay circuit which has a time constant sufficient to prevent single                       
             event transients from adversely affecting the logic circuit as recited in independent                    
             claim 6 and the claims grouped therewith, claims 7 and 8.                                                

                                                    ANALYSIS                                                          
                                RELATED TO OBVIOUSNESS REJECTIONS                                                     
                                           BASED UPON KONOPKIA                                                        
                    Independent claim 6 recites an RC delay circuit coupled to the comparator                         
             output … wherein the RC delay circuit has an RC time constant sufficient to                              

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