Appeal 2007-1572
Application 09/726,831
neither Crocker nor Nale teaches dedicated internal display RAM, dedicated
external display RAM, and display logic configured to manage and allocate
the two memories according to the display mode, (the display modes
including at least one of resolution modes and color modes), and Reddy,
asserted by the Examiner as supplying the missing teachings, fails to do so;
(b) there is no suggestion to combine the teachings of Crocker, Nale, and
Reddy; (c) Crocker teaches away from the teachings of Reddy, in that
Crocker specifically recites moving from a prior art system including
internal RAM and external RAM to a system having a single memory
module; and (d) the proposed combination of Reddy and Crocker would
change the principle of operation of Crocker, due to Reddy’s use of two
RAM modules in place of the single unified memory of Crocker.
The Examiner asserts that Crocker teaches an internal display RAM
and an external display RAM, controlled by the graphics processor 5
(Answer 3:19-20; see also FF 5), but that Crocker in combination with Nale
fails to explicitly teach or suggest that the memory includes an internal
RAM and an external RAM for allocating between the two (Answer 4:13-
15). The Examiner argues that the on-chip frame buffer 112 and off-chip
frame buffer 114 of Reddy meet the limitations of internal and external
display RAMs, both controlled by the graphics accelerator 110 (Answer 4:
17-18). According to the Examiner, the skilled artisan would have been
motivated to make the combination in order to increase display data retrieval
speed and reduce on-chip power dissipation (Answer 4:18–5:3). The
Examiner asserts that Crocker does not teach away from Reddy because
Crocker’s Figure 1 teaches that it is well known in the art that a separate
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