Appeal 2007-1756
Application 10/185,476
REJECTIONS AT ISSUE
Claims 1 through 4, 7 through 10, 19 through 23, 35, 36, 38 through
40, and 43 through 461 stand rejected under 35 U.S.C. § 102 (e) as being
anticipated by Kale. The Examiner’s rejection is set forth on pages 4
through 8 of the Answer. Claims 5, 6, 37, 41, and 422 stand rejected under
35 U.S.C. § 103 (a) as being unpatentable over Kale in view of Bass. The
Examiner’s rejection is set forth on pages 4 through 13 of the Answer.
Throughout the opinion, we make reference to the Brief (received
May 12, 2006), the Reply Brief (received August 31, 2006) and the Answer
(mailed July 27, 2006) for the respective details thereof.
ISSUES
Appellant contends that the Examiner’s rejection of claims 1 through
4, 7 through 10, 19 through 23, 35, 36, 38 through 40 and 43 through 46
under 35 U.S.C. § 102 (e) is in error. Appellant asserts that Kale does not
teach using the same instruction to write to both a memory associated with
the network processor and the memory associated with the host processor.
(Br. 10). With respect to claim 35, Appellant contends that “The suggestion
[in Kale] that various elements described can be different portions of the
1 We note that the statement of the rejection includes claims 37, 41 and 42
and does not include claim 36. However, the rationale supporting the
rejection discusses claim 36 but does not discuss claims 37, 41 and 42.
Accordingly, we consider claim 36 to be included in the rejection but not
claims 37, 41 and 42.
2 We note that the statement of the rejection does not include claims 41 and
42. However, the rationale supporting the rejection includes claims 41 and
42. Accordingly, we consider claims 41 and 42 to be included in the
rejection.
3
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