Appeal 2007-1756
Application 10/185,476
7) After the data transfer is complete the network processor
updates the descriptor tail pointer3 in the network processor
and writes to the set of network tail pointers in the host
processor’s memory. The network processor continues data
transfers until the tail and head pointers match. (Col. 5, l.
64- Col. 6, l. 15).
ANALYSIS
On the first issue, we disagree with the Examiner’s finding that Kale
teaches using the same instruction to write to both a memory associated with
the network processor and the memory associated with the host processor.
Independent claim 1 recites: “writing data associated with said message to a
memory associated with the network processor and to a memory associated
with a host processor coupled to said network processor using a single
network processor instruction to write to both memories.” Independent
claims 19 and 40 recite similar limitations. From the Examiner’s statements
on pages 14 and 15 of the Answer, it is unclear as to whether the Examiner
is relying upon Kale’s teaching of using a descriptor to transfer data to or
from host memory to meet the claimed single instruction writing to two
memories. As discussed in our findings of fact above, we find that Kale
teaches that a descriptor can be used to write to dis-continuous memory
locations. Facts 2 and 6. However, we do not find that Kale teaches that the
same descriptor performs a write to both the host processor memory and the
3 We believe the reference contains a typographical error and should read
updates the descriptor head pointer as the system performs data transfers
6
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