Appeal 2007-1756
Application 10/185,476
same network processor memory does not teach that they can be written to
both by the host processor and the network processor.” (Br. 11).
In response the Examiner states:
Kale discloses a method or “'technique' that provides improved data
transfer between a host processor, and one or more associated
'processing devices' (e.g. network processors) known as a Single
Descriptor Scatter Gather technique: The technique allows a 'single
descriptor' to be used to control the transfer of data to or from
multiple non-contiguous memory locations [col 3, lines 4-19]. Kale
discloses Steps A-E to accomplish the said 'technique' used to transfer
the data, as illustrated in Figure 3 [col 4, lines 19-30].
(Answer 15). Additionally, the Examiner finds that the limitation of using a
single network processor instruction to write to both memories is taught by
Kale‘s teaching that the host processor updates its own copy of the
descriptor head pointer in host descriptor table and also writes this value in
to the set of pointers of the network processor. (Answer 15-16). With
regard to claim 35, the Examiner finds that Kale teaches a storage that can
be written to by both a general purpose processor and a network processor.
Thus the contentions of Appellant and the Examiner present us with
two issues.
The first issue is whether Kale teaches using the same instruction to
write to both a memory associated with the network processor and the
memory associated with the host processor as recited in independent claims
1, 19 and 40. This issue does not apply to independent claim 35 as claim 35
does not recite a single instruction writing to two memories.
The second issue is whether Kale teaches a storage coupled to a
general purpose processor that can be written to by both a network processor
and a general purpose processor. This issue does not apply to independent
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Last modified: September 9, 2013