Appeal No. 95-2454
Application No. 07/396,733
Forming electrically isolated regions during the production of integrated circuits is not new in the
art. Applicant notes in the specification that electrical isolation has been achieved by surrounding the region
to be isolated with PN junctions. This structure is illustrated by the simplified and annotated version of
applicant’s Figure 1 below. In the figure the surrounding PN-junction is formed by the P+ isolation
“channels” or regions and the underlying PN junction.
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wherein the depth and shape of said depressions is selected such that the oxidized silicon has an upper
surface substantially coplanar with the top surface of said epitaxial silicon layer and a bottom surface which extends
through said epitaxial silicon layer to said PN junction, thereby both to surround each pocket by an annular-shaped
region of oxidized silicon and to electrically isolate each pocket by an annular-shaped region of oxidized silicon and a
portion of said laterally-extending PN junction.
25. The method of forming a plurality of electrically isolated pockets of semiconductor material in a
semiconductor structure comprising a silicon substrate of one conductivity type with an epitaxial silicon layer
thereon of said one conductivity type which comprises the steps of:
forming directly beneath portions of the top surface of said substrate low resistivity regions of opposite
conductivity type to said one conductivity type, such that a laterally-extending PN junction is formed between said
low resistivity regions and said silicon substrate;
growing a doped epitaxial silicon layer of said one conductivity type on said silicon substrate;
forming a layer of insulation on the top surface of said epitaxial silicon layer, said insulation having the
properties that it is substantially unaffected by at least one etchant used to remove epitaxial silicon and substantially
masks the diffusion of oxygen;
removing portions of said insulation overlying regions of said ~epitaxial silicon layer to be converted into
oxidized silicon;
forming depressions to a specified depth in said ~epitaxial silicon exposed by removal of said insulation by
removing part of said epitaxial silicon exposed by removal of said insulation; and subdividing said ~epitaxial silicon
layer into a plurality of electrically isolated pockets of semiconductor material by oxidizing the silicon exposed by
said depressions to form oxidized silicon;
wherein said depth is selected such that the oxidized silicon has an upper surface approximately coplanar
with the top surface of the remaining portions of said epitaxial layer and has a bottom surface in contact with said
laterally extending PN junction thereby to surround each pocket of semiconductor material by an annular-shaped
region of oxidized silicon.
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