Appeal No. 95-2454 Application No. 07/396,733 silicon oxide layer provides the electrical insulation while the polycrystalline semiconductor merely serves as a filler. Frouin, col. 2, lines 26-30. Frouin’s regions between the channels (actually surrounded by the channels) are electrically isolated by the PN junction and oxide layer on the channel surface. Frouin, col. 4, lines 7-9. One of the advantages of Frouin’s design is the reduction in the size of the “dead zone,” the required distance of separation of the various the components from the insulation channels. Frouin, col. 2, lines 46-50. Frouin also describes a process for manufacturing integrated circuits having filled isolation channels. E.g., Frouin, col. 5, line 30 - col. 6, line 17. Frouin’s process begins with a silicon substrate. An epitaxial layer of opposite conductivity-type is deposited on the substrate surface forming a PN junction. Frouin, col. 5, lines 30-35. Next the grooves are formed using etching and a photoresist technique. Frouin, col 5, lines 39-40. Etching using a photoresist technique includes using a layer which is substantially unaffected by at least one etchant used to remove the epitaxial silicon. The resulting grooves are then coated with10 an insulating material such as silicon dioxide “for which process a conventional technique can be used.” Frouin, col. 5, lines 41-44. Frouin also indicates that a silicon oxide layer can be applied by oxidation of the silicon. Frouin, col. 5, lines 62-63. Polycrystalline silicon is next deposited to fill the grooves. The deposition process not only fills the grooves but deposits a layer over the entire device. Frouin, col. 5, lines 44-55 and Figure 8c. The layer of polycrystalline silicon is then removed by grinding to obtain a flat surface. Frouin, col. 5, lines 56-57. This prepares the device for further processing and formation of active and passive circuit devices. Frouin, col. 5, lines 57 - col. 6, line 17. Frouin also notes that “the present 10 While not expressly disclosed by Frouin, the photoresist technique used in conjunction with etching was well known to those working in the art at the time of applicant’s invention. It involves placing a layer of light sensitive “photo-resist material” on to the substrate, exposing the layer to light having a pattern corresponding to the areas which are to be protected, developing the resist to harden the exposed areas, and stripping the unhardened areas to expose the areas to be etched. The mask of hardened photoresist is substantially unaffected by the etchant and thus allows for selective etching in forming the grooves. The hardened photoresist is then stripped. 8Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 NextLast modified: November 3, 2007