Appeal No. 95-2454
Application No. 07/396,733
The Frouin patent relates to integrated circuits having regions electrically isolated by means of filled
channels and a PN junction. Frouin, col. 1, lines 25-30. Frouin notes that electrical isolation of the type
disclosed in applicant’s Figure 1 has many drawbacks. Frouin, col. 1, lines 31-46. Frouin’s solution was
to form channels in the epitaxial layer which included insulating material. The channels extend from the free
surface layer and intersect the PN junction. Frouin, col. 2, lines 4-9. Frouin’s channels include a layer
of silicon oxide on the surface and the remainder of the channel is filled with a polycrystalline semiconductor
material. This structure is clearly shown in the semiconductor device shown in Frouin’s Figure 1. A
simplified and annotated version of Frouin’s Figure 1 is reproduced below.
The device includes a substrate, an epitaxial layer of a conductivity type which differs from the substrate’s
type, and isolation channels extending into the substrate past the PN junction. The grooves divide the
device into isolated islands or pockets. The grooves include an insulating surface oxide layer and are filled
with polycrystalline semiconductor material. The top of the grooves are essentially coplanar with the upper
surface of the epitaxial layer. Frouin, col. 3, lines 1-10. The insulating surface layer may be silicon oxide
and the polycrystalline semiconductor may be poly crystalline silicon. Frouin, col. 3, lines 57-61. The
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