Appeal No. 95-4957
Application 07/950,979
This is a decision on the appeal under 35 U.S.C. § 134
from the examiner's rejection of claims 1-6, 8, 10-19, 22, 24,
26-29, 34 and 35, which constituted all the claims remaining in
the application. An amendment after final rejection was filed on
September 26, 1994 and was entered by the examiner. This
amendment cancelled claim 26 so that it is not part of this
appeal.
The claimed invention pertains to an apparatus and method
for retrieving data from a system memory during a burst mode of
operation of a microcomputer.
Representative claim 1 is reproduced as follows:
1. A microcomputing system comprising:
a host bus;
a microprocessor, coupled to the host bus, the
microprocessor having a burst mode in which the microprocessor
engages in high speed consecutive data transfers;
a system memory, coupled to the host bus, the system memory
being in electrical communication with said microprocessor
through the host bus, the system memory including a plurality of
system memory data busses coupled to a plurality of bidirectional
latching transceivers, each system memory data bus being directly
coupled to the host bus through an associated bidirectional
latching transceiver from the plurality of bidirectional latching
transceivers; and
system memory controller means, coupled to the host bus and
to the system memory, for generating control signals and for
generating second addresses corresponding to data storage
locations to be accessed in the system memory during the burst
mode after receipt of a first host address from the
2
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