Appeal No. 95-4957
Application 07/950,979
We are unable to follow the examiner’s reasoning that the
addressing scheme of claim 1 is necessarily met by the pipeline
processing of Kronstadt. The examiner has found equivalence
between the burst mode transfer of data and the pipelining of
Kronstadt [supplemental answer, page 8]. We see no reason why
the memory controller of Kronstadt would have to generate any
addresses in addition to those received from the host processor
in pipelined fashion. In fact, the generation of “REAL ADDRESS”
between the CPU 10 and the memory controller 18 of Kronstadt
would suggest that the memory controller does not generate
additional addresses. There is no evidence in the record of this
case that any generation of second addresses is required in the
operation of the Kronstadt memory.
In summary, there are several differences between the
recitations of claim 1 and the teachings of Kronstadt which have
been asserted by appellants as patentably distinguishing over the
reference. The examiner has basically dismissed all these
differences as being inherent, equivalent or simply obvious. The
record does not support the examiner’s findings. Therefore, we
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