Appeal No. 95-4957
Application 07/950,979
reasons discussed above with respect to the plurality of data
busses.
Although we can agree with the examiner that the artisan
would have recognized the obviousness of using bidirectional
transceivers in place of bidirectional buffers, we cannot agree
with the examiner that Kronstadt in any way suggests using a
plurality of buffers or tranceivers for the latching of data. As
noted above, Kronstadt shows only a single data line feeding
either latch 26 of FIG. 4 or buffers 32 of FIG. 5. There is no
support for the examiner’s assertion that the claimed plurality
of bidirectional latching transceivers is inherently suggested by
the teachings of Kronstadt.
Appellants argue that Kronstadt does not teach a system
memory controller which generates addresses in the manner recited
in claim 1 [reply brief, page 4]. The examiner argues that
Kronstadt teaches a system memory controller 18 as shown in FIGS.
1, 3 and 4. With respect to the specific addressing arrangement
recited in claim 1, the examiner maintains that the pipelining
operation of Kronstadt meets the addressing arrangement of claim
1. In our view, although Kronstadt does broadly teach a system
memory controller, there is no suggestion in Kronstadt for the
functions performed by this element as recited in claim 1.
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