Ex parte KREIN et al. - Page 5




          Appeal No. 95-5030                                                          
          Application 07/815,694                                                      


          obviousness ground of rejection.  The arguments are based on the            
          following correct observations with regard to Fava and Miro.                
          Fava discloses a computer interconnect apparatus with a                     
          distributor through which information is passed between a                   
          plurality of elements.  Fava does not disclose storing                      
          information indicating the order in which information was                   
          received.  Instead, Fava discloses a round robin arbitration                
          scheme and does not send data in the order of receipt.                      
               With respect to Miro, the appellants note that while Miro              
          discloses a FIFO service queue to store disk drive I/O requests             
          (column 7, lines 51-54), the inputs to the FIFO service queue are           
          taken from a set of ten (10) holding queues each having a                   
          different assigned priority with respect to received I/O requests           
          (column 3, lines 37-68).  The appellants note (Br. at 12) that a            
          request directed to a given disk drive is entered into the                  
          particular holding queue having a service priority corresponding            
          to the priority class of tasks of such requests.  In that regard,           
          see column 3, lines 41-44, of Miro.  Items from the holding                 
          queues are moved to the FIFO service queue on the basis of                  
          priority classes rather than the time order of receipt in the               
          arbitration or control circuit.  On that basis, the appellants              
          argue that although Miro's control circuit includes a FIFO                  

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