Ex parte KATO et al. - Page 2

          Appeal No. 96-0950                                                          
          Application No. 07/727,932                                                  

          The claims                                                                  
               Appellants’ Claim 1 is illustrative of the invention                   
          involved in the present appeal:                                             
                    1.   A data gathering system in a parallel computer,              
                    said data gathering system comprising:                            
                         a common bus;                                                
                         a plurality of processors connected in parallel              
                    through said common bus,                                          
                              one of said plurality of processors being a             
                         reception processor which comprises a reception              
                         buffer for temporarily storing data gathered from            
                         other of said processors, and                                
                              said other processors of said plurality of              
                         processors being transmitting processors, each               
                         respective transmitting processor comprising:                
                                   a transmission buffer for temporarily              
                              storing the data to be transferred, and                 
                                   transfer control means for controlling             
                              data transmission from the transmission                 
                              buffer to said common bus by checking a                 
                              number of the data on said common bus, for              
                              sending a ready signal when ready to transfer           
                              the data and for determining an order of                
                              transfer by the respective transmitting                 
                              processor of said plurality of transmitting             
                              processors; and                                         
                         AND means for receiving the ready signals from               
                    said plurality of processors and for outputting a                 
                    reception signal to said plurality of processors.                 


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