Ex parte KATO et al. - Page 4

          Appeal No. 96-0950                                                          
          Application No. 07/727,932                                                  

          values are prestored in each transmitting processor’s transfer              
          control circuit as shown in Figure 14.  The transfer control                
          circuit checks the number of transfer data on the common bus L in           
          accordance with a predetermined transfer schedule, and waits for            
          an output from its own processor in accordance with the                     
          predetermined order.  Specification at 10, line 7 through 11,               
          line 4.  The order of transfer is prestored in the gathering                
          processor.  Specification at 12, lines 1-9.  In this way, the               
          scattered data are gathered in the correct sequence and do not              
          need to be rearranged by the gathering processor.  Specification            
          at 28, lines 9 through 34.                                                  
          The prior art                                                               
               Quinquis discloses a bus arbitration system in which each              
          processor has its own allocator as shown in Figure 1.  The                  
          allocator determines a priority code for itself, either at random           
          or by presetting.  Column 7, line 54 through Column 8, line 12.             
          The system uses a data bus for transmitting data between two                
          processors.  When multiple processors desire to transmit data,              
          they exchange control information over separate buses.  The                 
          control information present on the separate buses at any given              
          time reflects the priorities of the competing processors and                
          whether the data bus is or is not occupied.   Column 9, line 20             


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