Ex parte KATO et al. - Page 7

          Appeal No. 96-0950                                                          
          Application No. 07/727,932                                                  

          not check a number of the data being transferred on the data bus.           
          Furthermore, we do not find any suggestion in the cited art for             
          adding to Quinquis a transfer control means for checking a number           
          of data on the data bus as recited.  Quinquis has no need to                
          check a number of data on the data bus.                                     
                    2.   Means For Determining An Order of Transfer                   
               Each processor is recited as having transfer control means             
          for determining an order of transfer by the respective processor            
          among a plurality.  The examiner admits that Quinquis did not               
          teach such means.  Examiner’s Answer at 3 and 6-7.                          
               The examiner contends that it would have been obvious to               
          incorporate Katzman’s centralized transfer control means into               
          each of Quinquis’ processors because that would increase the                
          throughput of the Quinquis system by allowing the individual                
          processors to determine the order of transfer and thereby allow             
          parallel determination.  Examiner’s Answer at 7.                            
               The examiner cites nothing in the prior art to support the             
          stated rationale.  After carefully reviewing the cited art                  
          ourselves, we are unable to find any support or suggestion for              
          the proposed combination.  Katzman states that the bus controller           
          is preferably separate and distinct from the processors 33.                 
          Column 17, lines 37-40.  The bus controller and interprocessor              


Page:  Previous  1  2  3  4  5  6  7  8  9  10  11  12  13  14  Next 

Last modified: November 3, 2007