Appeal No. 97-0707
Application No. 08/001,474
With respect to claims 1 and 13, appellant argues that
Jaeckel does not teach a “dedicated address decoder corresponding
to each key address,” and a “memory element that includes . . .
multiple bit binary counters with each counter corresponding to a
separate bit position of information stored at each key address”
(Brief, pages 4 and 6). Figure 1 of Jaeckel shows an address
decoder 19 at each hard memory (i.e., key address) location. A
plurality of multiple bit binary counters C1 through CM are at
each hard memory location, and each multiple bit binary counter
corresponds to a separate bit position of information stored at
each hard memory location/key address. With respect to the
address decoders, Jaeckel explains that: “[f]or each implemented
memory location, which will be called a ‘hard memory location’,
there is an address decoder that determines whether or not to
activate that location during a read or a write operation”
(column 1, lines 48 through 51); “[t]he function of the address
decoder at each hard memory location is to compute the Hamming
distance between the given read or write address and the address
of the hard memory location” (column 2, lines 12 through 15);
“[o]ne way to implement the present invention relating to a
Sparse Distributed Memory is to implement the system by having an
address decoder for each hard memory location” (column 11, lines
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