Appeal No. 97-0707
Application No. 08/001,474
52 through 55); and “the address decoder for each hard memory
location has ten inputs,” and “if all ten match, the location is
activated” (column 13, lines 24 through 31). With respect to the
multiple bit binary counters, Jaeckel explains that: “[w]hen a
data word (a binary vector) is written to the memory at address
x, the word is added to the counters at each of the activated
hard memory locations” (column 2, lines 18 through 20); “[a]
computer memory system according to the invention includes a
plurality of hard memory locations in number equal to K, where K
is an integer greater than one, each hard memory location
comprising M counters, C1 through CM, where M is an integer
greater than zero” (column 4, lines 31 through 36); and “[f]or
each of the hard memory locations, there is a set of M counters,
. . . such as C1 through CM which are associated with hard memory
location 24" (column 12, lines 26 through 30).
In view of the foregoing, it is evident that Jaeckel
discloses all of the contested limitations of claims 1 and 13.
Thus, the 35 U.S.C. § 102(e) rejection of claims 1 and 13 is
sustained.
The 35 U.S.C. § 102(e) rejection of claim 5 is sustained
because “when performing a write operation” in Jaeckel, “[i]n the
case where the data is in the form of bits, the processor element
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