Ex parte CARY R. CHAMPLIN - Page 2




          Appeal No. 97-2111                                                          
          Application 08/158,345                                                      


          cancelled as the result of an amendment after final rejection               
          which was entered by the examiner.  Claims 16-19 are still                  
          pending in this application but stand withdrawn from                        
          consideration by the examiner as being directed to a nonelected             
          invention.                                                                  
          The claimed invention pertains to a method and apparatus                    
          for operating the Boundary-Scan master of a Boundary-Scan testing           
          apparatus.                                                                  
          Representative claims 20 and 21 are reproduced as                           
          follows:                                                                    
               20.  A method of operating a Boundary-Scan master coupled              
          to a data and control bus, said method comprising steps of:                 
               determining when an external test (EXTEST) instruction                 
          will assert a system action; and                                            
               requesting control of said data and control bus prior to               
          said assertion of said system action.                                       
               21.  A method as claimed in Claim 20 wherein:                          
               said Boundary-Scan master generates a test mode select                 
          (TMS) signal which controls Boundary-Scan testing of an                     
          integrated circuit (IC) having an instruction register and a test           
          access port (TAP) controller for operating in a plurality of                
          states, including an Exitl-DR state; and                                    
               said determining step comprises a step of identifying                  
          when said EXTEST instruction is loaded in said instruction                  
          register of said IC and said TAP controller has entered said                
          EXIT1-DR state.                                                             
          The examiner relies on the following references:                            

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