Appeal No. 95-0692
Application 07/755,237
Appellants have appealed to the Board from the examiner’s
final rejection of claims 1 to 6, which constitute all the
claims remaining in the application.
Representative claim 4 is reproduced below:
4. Apparatus for reserving a bus for data transfer in a
multi-processor data processing system containing a plurality
of data buses interconnecting a plurality of storage control
elements, wherein each of said storage control elements is
assigned a default data bus, said apparatus comprising:
token control logic means for passing a token from one
storage control element to another upon an occurrence of a
machine cycle; and
priority logic means for detecting a request for data
transfer from one of said storage control elements, said one
of said storage control elements being a requesting source,
said priority logic means reserving said requesting source’s
default data bus for said requested data transfer when all of
said plurality of data buses are not available until said
token is passed to said requesting source and at least one of
said data buses is available, said priority logic means
including means for avoiding a conflict between data buses,
wherein data to be transferred from one storage control
element to a second storage control element of said plurality
of storage control elements spends at least one machine cycle
in a data bus being used for the data transfer, and
wherein said priority logic means upon receipt of said
token by the requesting source, attempts to first reserve the
requesting source’s default data bus, but if the default data
bus is not available, said priority logic means then attempts
to reserve an alternate data bus.
2
Page: Previous 1 2 3 4 5 6 7 8 Next
Last modified: November 3, 2007