Appeal No. 95-1816
Application 07/859,347
1237, 1239 (Fed. Cir. 1995), cert. denied, 117 S.Ct. 80 (1996)
citing W. L. Gore & Assocs., Inc. v. Garlock, Inc., 721 F.2d
1540, 1548, 220 USPQ 303, 309 (Fed. Cir. 1983), cert. denied, 469
U.S. 851 (1984).
Appellants argue on pages 3 and 4 of the brief that Ito
fails to teach or suggest a processor comprising core circuitry
that executes instructions, bus control circuitry, memory
management circuit operable to transfer instructions and data
between the core circuitry and memory, clock generation circuitry
and a plurality of sense amplifiers in at least one of the core
circuity, the memory management circuitry, the bus control
circuitry and clock generation circuitry such that the plurality
of sense amplifiers are operable to compress logic thresholds to
increase logic switching speed as recited in Appellants’ claims.
Appellants further emphasize on page 2 of the reply brief that
Ito fails to teach or suggest a processor using sense amplifiers
to allow the processor to operate at a high clock rate with
reduced voltages as recited in Appellants’ claims.
Ito teaches a memory using sense amplifiers. However, Ito
fails to teach a processor capable of operating at a high clock
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