Appeal No. 95-1816
Application 07/859,347
rate with reduced operating voltages comprising core circuitry
that executes instructions, bus control circuitry, memory
management circuit operable to transfer instructions and data
between the core circuitry and memory, clock generation circuitry
and a plurality of sense amplifiers in at least one of the core
circuity, the memory management circuitry, the bus control
circuitry and clock generation circuitry such that the plurality
of sense amplifiers are operable to compress logic thresholds to
increase logic switching speed as recited in Appellants’ claims.
Ito teaches in column 1, lines 5-10, that the field of the
invention relates to a sense amplifier in a semiconductor memory.
Ito teaches in columns 4 and 5 a memory having a sense amplifier
connected to first and second bit lines for amplifying the
potential difference. Furthermore, we note that Ito only claims
in columns 6 through 8 a sense amplifier for amplifying a signal
stored in a memory cell for reading and a memory comprising a
sense amplifier connected to first and second bit lines of the
memory for amplifying the potential difference. Therefore, we
fail to find that Ito teaches a processor or a processor device
as recited in Appellants' claims.
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