Appeal No. 95-1816
Application 07/859,347
Furthermore, we fail to find any suggestion of modifying Ito
memory to provide a processor comprising core circuitry that
executes instructions, bus control circuitry, memory management
circuit operable to transfer instructions and data between the
core circuitry and memory, clock generation circuitry and a
plurality of sense amplifiers in at least one of the core
circuity, the memory management circuitry, the bus control
circuitry and clock generation circuitry such that the plurality
of sense amplifiers are operable to compress logic thresholds to
increase logic switching speed as recited in Appellants’ claims.
The Federal Circuit states that "[t]he mere fact that the prior
art may be modified in the manner suggested by the Examiner does
not make the modification obvious unless the prior art suggested
the desirability of the modification." In re Fritch, 972 F.2d
1260, 1266 n.14, 23 USPQ2d 1780, 1783-84 n.14 (Fed. Cir. 1992),
citing In re Gordon, 733 F.2d 900, 902, 221 USPQ 1125, 1127 (Fed.
Cir. 1984). "Obviousness may not be established using hindsight
or in view of the teachings or suggestions of the inventor."
Para-Ordnance Mfg., 73 F.3d at 1087, 37 USPQ2d at 1239, citing W.
L. Gore, 721 F.2d at 1551, 1553, 220 USPQ at 311, 312-13.
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