Appeal No. 95-4096
Application No. 08/188,660
This is a decision on appeal from the final rejection of
claims 2 through 4, the only claims pending in the
application.
The invention is directed to a packet switched bus for
carrying out memory transactions in a shared memory
multiprocessor. The packet switched bus handles multiple
memory transactions (e.g., read/write) in a time overlapping
manner, with each “request” followed at some later time by a
“reply.” These request/reply pairs are logically
disassociated, unlike in circuit switched bus systems which
involve master/slave relationships between the transaction
requester and the responders. In those systems, the master
maintains control of the bus from the time control is granted
until it receives a reply to its request.
The instant invention uses cache memory to enable each of
the processors and the I/O devices to cache addresses locally
that the devices are likely to be writing data to and/or
reading data from. Since this may mean that there could be
multiple copies of a given address at various sites within the
memory system, there must be some provision for avoiding the
potential problems of inconsistent data being employed. While
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