Appeal No. 95-4096
Application No. 08/188,660
accordance with selected ones of a predefined set of memory
transactions. Some of these transactions may cause multiple
copies of at least some of the data to be updated at different
times. The remainder of the claims contain recitations as to
what comprises the transactions and how the transactions are
selected as well as more details as to the request and reply
packets.
It may be that the claim language is rather broad but the
examiner should not confuse breadth with indefiniteness. See
In re Miller, 441 F.2d 689, 693, 169 USPQ 597, 600 (CCPA
1971).
We now turn to the rejection based on prior art. We will
not sustain this rejection as it is our view that the examiner
has not established a prima facie case of obviousness with
regard to the claimed subject matter.
The examiner cites Dashiell for the teaching of a shared
memory multiprocessor having a plurality of processors, I/O
devices and cache memories connected to a bus. However, as
the examiner recognizes, Dashiell does not disclose that the
bus is a packet switched bus, as claimed by appellants.
Accordingly, the examiner relies on Baxter for the suggestion
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