Appeal No. 95-4096
Application No. 08/188,660
the problem has been said to have been solved in circuit
switched bus systems by write back and invalidate data
consistency techniques, the instant invention is said to solve
the problem in packet switched bus systems by the use of
synchronous buses (shown as buses 15a-15i in Figure 1). By a
more efficient use of the available bus bandwidth, the buses
permit transactions to be performed using packets of differing
length, packet lengths being determined by logical
requirements of the transactions rather than by the timing
requirements of the bus.
Independent claim 2 is reproduced as follows:
2. In a shared memory multiprocessor having a main
memory, a plurality of processors, I/O devices, and respective
cache memories coupled to said processors and to said I/O
devices; the improvement comprising
a packet switched bus coupled to said main memory and to
said cache memories for transferring commands, memory
addresses, and data therebetween in compliance with selected
ones of a predefined set of memory transactions, including
transactions that cause multiple copies of at least some of
said data to be updated at different times under the control
of different ones of said processors;
each of said transactions being composed of a request
packet followed at an indeterminate later time by a reply
packet, thereby enabling the request and reply packets for
multiple transactions to be time interleaved on said bus;
3
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