Appeal No. 95-4096
Application No. 08/188,660
of a desirability to use a packet switched bus for bursty or
high speed data transfer and optimum utilization of resources.
The examiner then concludes that it would have been obvious to
use a packet switched bus in Dashiell in order “to achieve
efficient bursty or high speed data transfer and optimizing
the utilization of resources as suggested by Baxter” [answer-
page 5].
It is our view that the skilled artisan would not have
been led to substitute a packet switched bus for the MBUS 29
of Dashiell. Dashiell discloses a very specific system for
maintaining data consistency among distributed processors
wherein a cache memory associated with each processor accesses
data from another cache, if needed, or from real memory. When
a processor writes into a data word in the cache, the cache
will update all other caches that share the data before
allowing the write to the local cache. Thus, once a cache
gets control of the bus in Dashiell, it does not relinquish
control until all other caches have been updated, at which
time the cache releases the MBUS and writes data into its own
cell, setting its own master flag and updating its own LRU
stack [column 9, lines 23-28].
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