Appeal No. 95-4096
Application No. 08/188,660
If one were to substitute, for whatever reason, a packet-
switched bus for the MBUS of Dashiell, Dashiell’s operation
would appear to be inoperable. The data consistency sought by
Dashiell would not be achieved by the use of a packet-switched
bus since, as explained by Baxter, at column 5, lines 28-31,
“a packet-switched bus is a bus whose bandwidth is allocated
on a demand basis, as opposed to a circuit-switched bus, whose
bandwidth is allocated for the duration of the connection.”
Since the bus of Dashiell is not a packet-switched bus,
extensive modification of Dashiell would be necessary in order
to derive any operable system, such modification constituting
invention itself, wherein data consistency is maintained while
employing a packet-switched bus. This, of course, is
appellants’ invention.
Further, since Baxter is not concerned at all with the
use of cache memories or the maintenance of data consistency,
there seems to be no reason for the artisan to have been led
to employ the packet-switched bus of Baxter in a shared memory
multiprocessor system for maintaining data consistency. Where
is the suggestion to so employ Baxter’s packet-switched bus?
A mere reference, by Baxter [column 1, lines 16-17], to such a
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