Appeal No. 96-1549
Application 08/296,988
p-LAYER)." As best shown in Figure 3b, the buried p-type layer
has deeper portions or dimples which fill in the holes in the n-
type grid and has shallower portions which overlie the n-type
material of the grid. Figure 6 shows that when this arrangement
is used in a DRAM cell, the n-type grid and p-type layer are
positioned such that the deeper portions or dimples of the p-type
layer lie under the n-type bit lines and FET channels, where
capacitance is to be minimized, and the shallower portions of the
p-type layer lie under the storage nodes, where an increase in
capacitance is desirable (Wordeman at 42-43).
Appellant argues that Wordeman's buried p-type layer fails
to satisfy the claim in two respects, the first being that
Wordeman does not teach that the buried p-layer by itself "would
be adequate to substantially reduce the soft-error rate, as
taught by the present invention" (Br. at 7). This argument fails
because the claim language "formed to stop " particles" does not
require that substantially all " particles be stopped and because
Wordeman discloses (at 41, 2d col., item 3) that the p-type layer
. . . blocks the radiation-generated minority carriers from
diffusing up through the [grid] holes (due to the field in
the high-low junction formed between the low doped substrate
and the high p-doping in the hole). These carriers diffuse
sideways to be collected in the n-grid.
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